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ARM
- 作为一种16/32 位的高性能、低成本、低功耗的嵌入式RISC微处理器，ARM微处理器 目前已经成为应用最为广泛的嵌入式微处理器。 本书在全面介绍ARM处理器的体系结构、编程模型、指令系统和开发工具的同时，以 Samsung 公司的一款基于以太网系统的ARM处理器－S3C4510B 为核心，详细讲解系统的 设计、调试，以及相关的软件设计和嵌入式操作系统的移植过程。通过阅读本书，可以使具 备一定的系统设计能力的读者全面掌握开发基于ARM微处理器系统的多方面知识，从而具 备
smdk2413_application_note_rev10
- SMDK2413 (Samsung MCU Development Kit) for S3C2413X is a platform that is suitable for code development of SAMSUNG s S3C2413X 16/32-bit RISC microcontroller (ARM926EJ-S) for hand-held devices and general applications. The S3C2413X consists of 16-/32-
LM3S615_cn
- LM3S615 微控制器包含以下的产品特性： 32 位RISC 性能 － 采用为小型嵌入式应用方案而优化的32 位ARM® CortexTM M3 v7M 结构 － 可兼容Thumb® 的Thumb-2 专用指令集处理器内核，可提高代码密度 － 50-MHz 工作频率 － 硬件除法和单周期乘法 － 集成了嵌套向量中断控制器（NVIC）以提供明确的中断处理 － 29 个中断，带8 个优先级 － 存储器保护单元（MPU）为受保护的操作系
arm-gcc-3.4.4-gm8180.tar.bz2
- GM’s GM8180 MDC1 hardware environment is a highly efficient RISC-based platform for the purpose of verifying and evaluating AMBA-based designs in the early development stage. The complete set of MDC1 GM8180 platform consists of a main board (MB12
BuildingPaPRISCPSystemPinPanPFPGA
- 一个32位 RISC CPU 核心，由Verilog 编写而成-A 32-bit RISC CPU core, written by Verilog
CPU_test
- 设计并通过modelsim仿真软件实现了一个可以在FPGA平台上运行的8位RISC的CPU软核-Design an 8-bit RISC CPU soft core on an FPGA platform and simulate it using ModelSim
Amber_ARM-compatible_core_latest.tar
- The Amber processor core is an ARM-compatible 32-bit RISC processor. The Amber core is fully compatible with the ARM ® v2a instruction set architecture (ISA) and is therefore supported by the GNU toolset. This older version of the ARM instr
tx79architecture
- Toshiba TX System RISC TX79 Core Architecture (Symmetric 2-way superscalar 64-bit CPU) Rev. 2.0 This user’s manual describes the C790 superscalar microprocessor for the system designer, paying special attention to the software interface and th
axi_ipif_v2.3
- The AXI4-Lite IP Interface (IPIF) is a part of the Xilinx family of Advanced RISC Machine (ARM) Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) control interface compatible products. It provides a point-to-point
freedom-master
- This is a feedom master version of the RISC-V core and can be used with LGPL license
Insiders_Guide_XC166
- The C166S V2 CPU core used in the XC166 seriesmakes extensive use of Reduced Instruction Set Computer (RISC) concepts to achieve its blend of very highperformance at modest cost.